Low audible noise power supply method and controller therefor

ABSTRACT

A power controller forms drive pulses that reduces audible noise under light load conditions.

BACKGROUND OF THE INVENTION

The present invention relates, in general, to electronics, and moreparticularly, to methods of forming semiconductor devices and structure.

In the past, the semiconductor industry utilized various methods andcircuits to implement switching power supply systems and controllers. Inorder to minimize power dissipation, some implementations would switchthe power transistor at a lower frequency or may even switch the powertransistor on and off in short bursts. One such implementation tominimize power dissipation was disclosed in U.S. Pat. No. 6,252,783issued to Dong-Young et al on Jun. 26, 2001.

One problem with such implementations was audible noise typically in thefrequency range of about twenty to twenty thousand (20-20,000) Hz. Whenthe switching frequency of the power transistor was reduced, it oftenproduced noise in the audible frequency range. The audible noise wasoften objectionable and became a nuisance to users of the power supply.

Accordingly, it is desirable to have a switching power supply that hasreduced power dissipation, and that minimizes audible noise.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates a portion of an embodiment of a powersupply system having a power supply controller in accordance with thepresent invention;

FIG. 2 is a graph illustrating timing diagrams for a portion of thesignals and operation sequence of the power supply controller of FIG. 1in accordance with the present invention;

FIG. 3 schematically illustrates a portion of another embodiment of apower supply system having a power supply controller in accordance withthe present invention;

FIG. 4 is a graph illustrating timing diagrams for some signals presentin prior power supply controllers; and

FIG. 5 schematically illustrates an enlarged plan view of asemiconductor device that includes a power controller in accordance withthe present invention.

For simplicity and clarity of illustration, elements in the figures arenot necessarily to scale, and the same reference numbers in differentfigures denote the same elements. Additionally, descriptions and detailsof well-known steps and elements are omitted for simplicity of thedescription. As used herein current carrying electrode means an elementof a device that carries current through the device such as a source ora drain of an MOS transistor or an emitter or a collector of a bipolartransistor, and a control electrode means an element of the device thatcontrols current through the device such as a gate of an MOS transistoror a base of a bipolar transistor.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates an embodiment of a portion of a powersupply system 10 that includes a power supply controller 21 whichminimizes audible noise during the operation of both controller 21 andsystem 10. Other components typically are connected externally tocontroller 21 in order to provide functionality for system 10. Forexample, a bridge rectifier 11 which receives a source voltage from anac source such as a household mains, a transformer 12, a blocking diode13, an energy storage capacitor 14, an output transistor 47, a feedbacknetwork 18, and a current sense resistor 19 typically are connectedexternally to controller 21. Transistor 47 typically is a switchingpower transistor that is connected in series between one leg of theprimary of transformer 12 and resistor 19, although in some embodimentstransistor 47 and resistor 19 may be included within controller 21.Transformer 12 typically includes a secondary winding 80 that along witha bias resistor 81, a blocking diode 85, and a storage capacitor 82 areused to provide power for operating controller 21. Controller 21receives the power between a voltage input 61 and a voltage return 64,and system 10 provides an output voltage between output terminals oroutputs 16 and 17. A load 15 typically is connected between outputs 16and 17 to receive a load current from system 10 in addition to theoutput voltage.

Controller 21 has an output 65 that is connected to drive transistor 47.Current sense resistor 19 is connected in series between transistor 47and return 64 to provide a current sense (CS) signal at a node 67 thatis a voltage which is representative of a switch current 48 that flowsthrough transistor 47. The current sense (CS) signal is received bycontroller 21 on a current sense (CS) input 62. Feedback network 18typically is an optical coupler that provides a current 68 that isrepresentative of the output voltage between outputs 16 and 17. Theoptical coupler typically has a light emitting diode connected betweenoutput 16 and a connection 20 to a reference voltage, and an opticaltransistor having a collector connected to a feedback (FB) input 63 ofcontroller 21 and an emitter connected to return 64. Reference voltagereceived at connection 20 is chosen so the value of the referencevoltage and the voltage drop across the diode of network 18approximately equals the nominal value of the output voltage betweenoutputs 16 and 17. For example, the reference voltage could be a zenerdiode connected between output 17 and connection 20. Current 68 isreceived by controller 21 and is converted to a FB voltage at input 63by a resistor 25. The optical coupler of network 18 and resistor 25invert the operation of the FB voltage so that the FB voltage increasesas the output voltage decreases and vice versa. Feedback network 18 mayalso be any one of a variety of well known feedback circuits includingseries connected resistors. Transformer 12, capacitor 14, diode 13, andnetwork 18 are shown to assist in describing the operation of controller21. In most embodiments, network 18, transistor 47, transformer 12,capacitor 14, and diode 13 are external to the semiconductor die onwhich controller 21 is formed.

Controller 21 includes a pulse width modulated (PWM) controller or PWM22, a reference generator or reference 26, a signal envelope controlblock 40, and an internal regulator 23. Controller 21 also may includeother circuits to provide additional functionality to controller 21 suchas an under voltage lock-out (UVLO) circuit 24, a leading edge blankingcircuit (LEB) 27, a UVLO control logic OR gate 44, and a transistordriver 46. Other well-known functions such as soft-start andover-voltage protection may also be included within controller 21.Regulator 23 provides an operating voltage for the elements withincontroller 21 including PWM 22, block 40, UVLO circuit 24, and LEB 27.Although not shown for simplicity of the drawings, regulator 23 isconnected between input 61 and return 64 to receive the input voltageapplied to input 61. PWM 22 includes a clock generator or clock 41 thatprovides clock signals at a periodic rate, a reset dominate RS latch 42,a burst-mode comparator 39, a PWM comparator 34, and a logic control ORgate 43.

Controller 21 is formed to operate in at least two different stableregulated modes referred to herein as a normal-mode and a burst-mode,and to transition between these two modes in response to load currentchanges. The output of comparator 39 is used to switch controller 21between the normal and burst operating modes responsively to the FBvoltage changing from a first value to a second value. In thenormal-mode, controller 21 regulates the output voltage to a desiredoutput voltage value while supplying a normal average load current toload 15. To facilitate this, PWM 22 provides periodic drive pulses totransistor 47. PWM 22 controls the duration or width of the drive pulsesand correspondingly the duration and the amplitude of switch current 48responsively to the value of the FB voltage and the CS signal. Underlight load conditions the load current required by load 15 may decrease.In such a case, it may be desirable to reduce the number of drive pulsesto transistor 47 in order to improve the efficiency of system 10.Controller 21 is formed to detect such a light load condition and changethe operating mode of controller 21 to the burst-mode. In theburst-mode, controller 21 reduces the average value of the load currentsupplied to load 15 in response to the decreased load current requiredby load 15 but continues regulating the output voltage to the desiredoutput voltage value. In the burst-mode, controller 21 provides sets ofdrive pulses to transistor 47 and controls the width of the drive pulseswithin each set to form an asymmetric signal envelope for each of thecorresponding sets of pulses of switch current 48 in order to reduceaudible noise.

FIG. 2 is a graph having plots that illustrate some signals generatedduring the operation of controller 21. The abscissa indicates time andthe ordinate represents the value of either current or voltage. A plot71 represents the value of a shifted FB voltage as is explained furtherhereinafter and a plot 72 represents switch current 48 flowing throughtransistor 47 in response to drive pulses that are generated at output65 of controller 21. A plot 73 represents the signal envelope of switchcurrent 48 that is generated when PWM 22 is operating in the burst-mode.A plot 74 represents the value of a FB reference voltage received on aninverting input of comparator 34. Between time T0 and T1, controller 21is regulating in the normal-mode. The time between T1 and T2 is atransition time when controller 21 is switching from the normal-mode tothe burst-mode in response to a load current change. Between time T2 andT7, controller 21 is regulating in the burst mode. During times T2 toT3, T4 to T5, and T6 to T7 controller 21 is skipping pulses in the burstmode. Between time T7 and T8 controller 21 is in transition betweenregulating in the burst-mode and regulating in the normal-mode inresponse to a load current change. After time T8, controller 21 isregulating in the normal-mode. Note that plot 73 illustrates the signalenvelope during the burst-mode, thus, there is not a waveshape betweentimes T0-T1 and T7-T8.

This description has references to both FIG. 1 and FIG. 2. The exemplaryembodiment illustrated in FIG. 1 and particularly the embodiment ofblock 40 is used for the description of the operation of controller 21,however, other embodiments may use different implementations to achievethe desired asymmetrical signal envelope of switch current 48 during theburst-mode of operation as is described hereinafter. Block 40 includesan envelope generator 59, a clamp reference 28, and a shunt regulatorclamp 36. Envelope generator 59 is formed to generate an envelope signalon an output 60. The envelope signal is used to control the waveshape orsignal envelope of switch current 48 when controller 21 is operating inthe burst-mode. In the preferred embodiment, generator 59 includes abias transistor 56, an output transistor 54, a timing capacitor 53, acontrol transistor 49, and current mirror transistors 51 and 52connected in a current mirror configuration. Clamp reference 28preferably includes a follower transistor 31 and a pull-down resistor33. Shunt regulator clamp 36 preferably includes an amplifier 37 and atransistor 38 connected in a shunt regulator configuration. Othercircuit configurations can be used to implement block 40 as long as theembodiments achieve an asymmetric signal envelope of switch current 48during the burst-mode of operation.

Reference 26 provides three reference voltages, Vref1 through Vref3, onthree separate outputs that are used in the operation of controller 21.Vref1 is a bias voltage that is received by generator 59 to provide biascurrents within generator 59 and may also be used to provide other biascurrents that are not shown for simplicity of the drawing. Vref3 isreceived by comparator 39 and is used to set a threshold voltage atwhich controller 21 begins operating in the burst-mode as will be seenfurther hereinafter. Vref2 is used by reference 28 to set a maximumvalue of the signal envelope as will be seen further hereinafter.Typically, Vref2 has a higher voltage value than Vref3.

During operation in the normal-mode, the output voltage between outputs16 and 17 is close to a first value or desired operating output voltagevalue. The value of the resulting FB voltage received on input 63 isshifted through resistors 83 and 84 to generate the shifted FB voltage.The desired value of the output voltage is established by the shifted FBvoltage and the CS signal. The desired value of the shifted FB voltagefor a normal load current to load 15 typically is between Vref2 andVref3. Since the FB voltage is greater than Vref3, the output ofcomparator 39 is low. The low output of comparator 39 is received bygate 43 and allows the output of PWM comparator 34 to control latch 42through gate 43. The low output of comparator 39 also enables envelopegenerator 59 by disabling transistor 49 through inverter 57. Thus, theenvelope signal on output 60 is high. The high envelope signal isreceived on a control input 30 of reference 28 and correspondinglyenables transistor 31. Reference 28 responsively couples Vref2 to anoutput 29 of reference 28 to generate an envelope control signal onoutput 29 that is approximately equal to Vref2. Clamp 36 receives boththe envelope control signal from reference 28 and the shifted FB voltageand responsively generates the FB reference voltage on output 35. Sinceamplifier 37 and transistor 38 are connected as a shunt regulator, aslong as the envelope control signal is greater than the shifted FBvoltage, clamp 36 forms the FB reference voltage to be approximatelyequal to the shifted FB voltage, thus, the FB reference voltage on anoutput 35 is approximately equal to the shifted FB voltage asillustrated by plot 74 between time T0 and T2. In the event of a shortcircuit or other failure on output 16, clamp 36 ensures that the valueof the FB reference voltage is never greater than Vref2, therebylimiting peak switch current, in order to prevent damaging system 10.

Clock 41 provides clock pulses that set latch 42 and enable or turn-ontransistor 47 through driver 46 causing current 48 to flow throughtransistor 47 and generate the CS signal. When the value of the CSsignal on input 62 increases to a value equal to the FB referencevoltage on output 35, the output of PWM comparator 34 goes high to resetlatch 42 and turn-off or disable transistor 47. This is illustrated byplot 72 between time T0 and T2. Each pulse of current 48 in plot 72between time T0 and T2 begins when clock 41 sets latch 42. The width ofeach drive pulse to transistor 47, thus the width and the resultingamplitude of each pulse of switch current 48, is set by the value of theFB reference voltage and the CS signal. The greater the width of thedrive pulse on output 65, the greater the amplitude and the width ofboth switch current 48 and the load current to the combination of load15 and capacitor 14.

When a light load condition occurs, the amount of load current used byload 15 decreases. Due to the time delay through system 10, PWM 22temporarily continues to supply a larger load current causing acorresponding increase in the output voltage on output 16 from the firstvalue or desired value to a second value resulting in an increase incurrent 68 and a corresponding decrease in the FB voltage at input 63.When the FB voltage decreases to the threshold value of comparator 39 ora second voltage value, the output of comparator 39 is driven highindicating the beginning of operation in the burst-mode. The shifted FBvoltage typically decreases to a threshold value that is no greater thanVref3 as illustrated by plot 71 at time T2. In the burst-mode, PWM 22groups drive pulses to transistor 47 and the corresponding pulses ofcurrent 48 into sets with each set of pulses of current 48 having anasymmetric signal envelope. The shape of the signal envelope and theamplitude of the pulses of current 48 within each set are controlled bythe shape of the envelope signal formed by generator 59. In thepreferred embodiment, generator 59 generates a ramp or slope ortriangular shaped asymmetrical waveshape that increases over time froman initial value to a greater value and then rapidly decreases back tothe initial value. Thus, PWM 22 is coupled to receive the asymmetricalreference voltage from block 40 and responsively generate a set of drivepulses having widths suitable for forming a set of pulses of current 48that have an asymmetrical signal envelope. Clamp reference 28 is formedto receive the asymmetric waveshape of the envelope signal andresponsively generate an envelope control signal on output 29 thatfollows the waveshape of the envelope signal from generator 59. Clamp 36receives the envelope control signal and the shifted FB voltage andresponsively generates a FB reference voltage on output 35 that has thesame waveshape as the envelope signal formed by generator 59. Thistriangular or ramp shaped asymmetrical waveform is used to control thewidth of the drive pulses on output 65 and the corresponding signalenvelope, width, and amplitude of the pulses of current 48. The specificimplementation of generator 59 illustrated in FIG. 1 is one example of acircuit capable of generating the preferred asymmetrical signal envelopeof current 48. However, it should be noted that other circuits may beutilized to form the preferred signal envelope and that otherasymmetrical shaped signal envelopes may be utilized. The asymmetricwaveshape facilitates reducing audible noise during the burst-modeoperation. Each pulse of current 48 within each set of current pulsesstarts when latch 42 is set by clock 41 and ends when the value of theCS signal and the FB reference voltage cause the output of comparator 34to go high.

For the example embodiment illustrated in FIG. 1 and FIG. 2, at time T2the FB voltage reduces to a value less than Vref3 and drives the outputof comparator 39 high. The output of comparator 39 resets latch 42through gate 43 to terminate drive pulses on output 65. The high alsoenables transistor 49 through inverter 57 causing current to flowthrough transistor 49 and pull node 58 low. Output 60 is thereby drivento the gate-to-source voltage of transistor 54. The source voltage offollower transistor 31 of reference 28 and output 29 follows the sourcevoltage of transistor 54 and is pulled low through resistor 33. The lowon output 29 forces the FB reference voltage on output 35 low. When theFB voltage increases to a value equal to or greater than Vref3 asillustrated at time T3, the output of comparator 39 goes low. The lowallows comparator 34 to control gate 43 and latch 42, and also turns-offtransistor 49 of generator 59 to begin charging capacitor 53. Ascapacitor 53 charges, output 60 increases from a low value approximatelyequal to return 64 plus the Vgs of transistor 54 toward the value ofVref2. The Vgs of transistor 54 shifts the level of the envelope signalon output 60 to compensate for the Vgs drop of follower transistor 31.Therefore, the voltage on output 29 is approximately equal to thevoltage on node 58. The output 29 increases from a low valueapproximately equal to return 64 toward the value of Vref2. Sinceamplifier 37 and transistor 38 are connected as a shunt regulator andthe envelope control signal is less than the shifted FB voltage, the FBreference voltage on output 35 correspondingly increases from a lowvalue approximately equal to return 64 toward the value of Vref2 asillustrated by plot 74 between time T3 and T4. Thus, the FB referencevoltage on output 35 follows the waveshape of the envelope signal onoutput 60.

Each clock pulse of clock 41 sets latch 42 thereby enabling transistor47 and causing a pulse of current 48 unless latch 42 is held reset bygate 43. The corresponding CS signal from node 67 is received bycomparator 34. When the value of the CS signal increases to the value ofthe FB reference voltage on output 35, the output of comparator 34 goeshigh resetting latch 42. The FB reference voltage continues to increase,thus, the next clock pulse from clock 41 generates another pulse ofcurrent 48 that has a longer duration due to the increased value of theFB reference voltage. As the FB reference voltage increases, eachsuccessive pulse of current 48 flows for a longer period of time therebyachieving a greater amplitude according to the equation (V/L)=(dI/dT),where V is the voltage across the primary inductance of transformer 12,L is the value of the primary inductance, dI is the peak-to-peak chargein primary current 48, and dT is the change in time, as illustrated bythe pulses of current 48 within the set of pulses illustrated by plot 72between time T3 and T4. At time T4, the FB voltage decreases to a valueless than Vref3 and the output of comparator 39 again goes low. The lowoutput of comparator 39 resets latch 42 through gate 43 and terminatesthe pulse of current 48. The low output of comparator 39 also enablestransistor 49 which drives node 58 low. Resistor 33 responsively pullsoutput 29 low as the source of follower transistor 31 follows node 58causing output 35 to also go low and drive the output of comparator 34high ensuring that transistor 47 is disabled. Consequently, it can beseen that during the burst-mode the waveshape of the envelope signalfrom generator 59, thus the amplitude and waveshape of the FB referencevoltage on output 35, controls the amplitude of each pulse of current 48as illustrated by plot 72 between T3 and T4. As the amplitude of theenvelope signal on output 60 increases, the amplitude of each successivepulse of current 48 also increases. Thus, the amplitude of the pulses ofcurrent 48 and the resulting shape of the signal envelope is controlledby the amplitude and shape of the asymmetrical FB reference voltage.

The sequence repeats each time that the FB voltage increases to thethreshold value of comparator 39 causing controller 21 to generateanother set of pulses of current 48 as illustrated between time T5 andT6. Typically, the sets are spaced apart at least a time periodapproximately equal to the period of one pulse of clock 41.

If load 15 begins requiring more power, the output voltage decreasescausing a corresponding increase in the FB voltage. The increasing FBvoltage keeps the output of comparator 39 low allowing output 60 ofgenerator 59 to increase in value as capacitor 53 charges toward theoperating voltage from regulator 23. The FB reference voltage on output35 correspondingly increases toward Vref2 until reaching the value ofthe shifted FB voltage as illustrated by plot 74 after time T7. As longas the FB voltage remains greater than Vref3, the output of comparator39 remains low and the FB reference voltage continues to increase untilthe envelope control signal on output 29 is greater than the shifted FBvoltage. At that time, the FB reference voltage begins following theshifted FB voltage. If the value of the shifted FB voltage were greaterthan Vref2, for example a short circuit occurred between outputs 16 and17, clamp 36 would clamp the value of the FB reference voltage to Vref2.A dashed line extension illustrates the continued charging of capacitor53 and output 60.

In order to facilitate this functionality of controller 21, a gate oftransistor 56 is connected to the Vref1 output of reference 26, a sourceof transistor 56 is connected to the output of regulator 23, and a drainis commonly connected to output 60 and the drain and gate of transistor54. The source of transistor 54 is commonly connected to the drain oftransistor 52 and a first terminal of capacitor 53. A second terminal ofcapacitor 53 is commonly connected to the drain and gate of transistor51 and the gate of transistor 52. The sources of transistors 51 and 52are commonly connected to return 64. Transistor 49 has a sourceconnected to the source of transistor 56, a drain connected to thesecond terminal of capacitor 53, and a gate connected to an output of aninverter 57. An input of inverter 57 is commonly connected to the outputof comparator 39 and a first input of gate 43. A non-inverting input ofcomparator 39 is connected to the Vref3 output of reference 26. Aninverting input of comparator 39 is connected to input 63, a firstterminal of resistor 25, and a first terminal of resistor 83. A secondterminal of resistor 25 is commonly connected to the output of regulator23. A second terminal of resistor 83 is commonly connected to anon-inverting input of amplifier 37, a first terminal of resistor 84,and a drain of transistor 38. A second terminal of resistor 84 and thesource of transistor 38 are commonly connected to return 64. An outputof amplifier 37 is connected to the gate of transistor 38. A drain oftransistor 38 is connected to output 35 and to an inverting input ofcomparator 34. An inverting input of amplifier 37 is commonly connectedto a first terminal of resistor 33 and a source of transistor 31. Asecond terminal of resistor 33 is connected to return 64. A drain oftransistor 31 is connected to the Vref2 output of reference 26, and agate is connected to an input 30 and to output 60. A non-inverting inputof comparator 34 is connected to receive the CS signal from input 62through LEB 27. An output of comparator 34 is connected to a secondinput of gate 43, and an output of gate 43 is connected to the resetinput of latch 42. A set input of latch 42 is connected to the output ofclock 41 and the inverting output of latch 42 is connected to an inputof driver 46 through Gate 44. An output of driver 46 is connected tooutput 65. In some embodiments, output 65 is connected to a gate oftransistor 47. In some embodiments, generator 59 may be a portion of asoft-start circuit of controller 21.

FIG. 3 schematically illustrates an embodiment of a portion of a powersupply system 95 that is an alternate embodiment of system 10illustrated in FIG. 1. System 95 includes a PWM controller or PWM 97that operates controller 21 as a voltage mode controller. PWM 97includes a clock 96 that provides a ramp signal in addition to the clocksignal provided by clock 96. In the normal-mode of operation, the rampsignal is used by PWM 97 to provide the PWM voltage mode regulation.Such voltage mode regulation is well known in the art. In theburst-mode, the FB reference voltage controls the signal envelope ofcurrent 48.

FIG. 4 is a graph having plots that illustrate some of the signalsgenerated during the operation of a typical prior controller. Theabscissa indicates time and the ordinate represents values. A plot 76represents the value of the feedback voltage and a plot 77 representsswitch current pulses that are generated in response to thecorresponding feedback voltage. A plot 78 represents the signal envelopeof the switch current pulses that are generated in a skip cycle mode. Ascan be seen between times T2 and T3, the prior controller generates anumber of switch current pulses having an amplitude controlled by the FBvoltage amplitude and then skips cycles until a time T4 when the outputvoltage again decreases and another set of switch current pulses arerequired. This operation continues and repeats as long as the feedbackvoltage is below the threshold voltage. Plot 78 indicates the shape ofthe signal envelope that is generated by each set of pulses that aregenerated in the skip cycle mode. It is easily seen that the signalenvelope generated by the sets of drive pulses has a shape that hasvertical or square edges and is approximately symmetrical about themidpoint for the examples shown in FIG. 4, and is nearly a rectangularwave shape.

It can be shown by mathematical analysis through a Fourier transformthat the rectangular shape of the symmetrical signal envelope shown byplot 78 in FIG. 4 produces signals in the audio range that have a largeramplitude than the audio range signals produced by the asymmetricalsignal envelope produced by controller 21. Additionally, themathematical analysis also shows that the rectangular shape of thesymmetrical signal envelope shown by plot 78 in FIG. 4 produces higherfrequency harmonics than the asymmetrical signal envelope produced bycontroller 21. Reducing the higher frequency harmonics results insimpler and lower-cost filtering thereby reducing the system cost.

FIG. 5 schematically illustrates an enlarged plan view of a portion ofan embodiment of a semiconductor device 90 that is formed on asemiconductor die 91. Controller 21 is formed on die 91. Die 91 may alsoinclude other circuits that are not shown in FIG. 5 for simplicity ofthe drawing. Controller 21 is formed on die 91 by semiconductormanufacturing techniques that are well known to those skilled in theart.

In view of all of the above, it is evident that a novel device andmethod is disclosed. Included, among other features, is forming a powercontroller to generate a set of drive pulses to a transistor thatresponsively forms a set of pulses of current having an asymmetricalenvelope signal envelope. The asymmetrical envelope results in lessaudible noise and lower amplitude harmonics than other signal envelopes.

While the invention is described with specific preferred embodiments, itis evident that many alternatives and variations will be apparent tothose skilled in the semiconductor arts. More specifically the inventionhas been described for a particular signal envelope control blockembodiment and for particular connections to a PWM control section,although the method is directly applicable to other embodiments forgenerating the asymmetrical signal envelope.

1. A method of forming a power system controller comprising: coupling aPWM controller to receive a reference signal having an asymmetricalwaveform that increases continuously over a time interval that isgreater than a switching cycle of a drive pulse formed by the PWMcontroller and responsively generate during the time interval a set ofdrive pulses having a plurality of drive pulses with increasing widths;and operably coupling the PWM controller to use the plurality of drivepulses during the time interval to control a power switch to form aplurality of current pulses having successively increasing amplitudesresponsively to the increases in the reference signal wherein thesuccessively increasing amplitudes form an asymmetrical signal envelopefor the current pulses.
 2. The method of claim 1 further includingcoupling a control block to generate the reference signal having theasymmetrical waveform responsively to a control signal representative ofan output voltage increasing from a first value to a second value. 3.The method of claim 2 wherein coupling the control block to generate thereference signal includes coupling the control block to generate atriangular shaped reference signal.
 4. The method of claim 3 whereincoupling the control block to generate the triangular shaped referencesignal includes coupling the control block to generate the triangularshaped reference signal having a vertical cut-off.
 5. The method ofclaim 1 wherein coupling the PWM controller to receive the referencesignal includes coupling a comparator of the PWM controller to receivethe asymmetrical reference signal.
 6. The method of claim 1 whereincoupling the PWM controller to receive the reference signal includescoupling the PWM controller to receive the asymmetrical reference signaland responsively generate each drive pulse within the set with a widththat is greater than a previous drive pulse within the set.
 7. A methodof forming a power supply controller comprising: configuring the powersupply controller to organize output drive pulses of the power supplycontroller into a plurality of sets with each set having a plurality ofdrive pulses wherein the plurality of sets are spaced apart in time;configuring the power supply controller to form a reference signalhaving a value that varies continuously over a time interval that isgreater than at least two drive pulse cycles of the plurality of drivepulses; and configuring the power supply controller to form theplurality of drive pulses within at least one set during the timeinterval to have successively increasing pulse widths in order togenerate successive current pulses that increase in amplitude and forman asymmetrical signal envelope for the successive current pulseswherein at least a portion of the asymmetrical signal envelop increasesin amplitude responsively to the increase in the amplitude of thesuccessive current pulses.
 8. The method of claim 7 wherein configuringthe power supply controller to form the plurality of drive pulsesincludes configuring the power supply controller to form the pluralityof drive pulses within the at least one set to have widths suitable togenerate an asymmetrical signal envelope for the current through atransistor that receives the plurality of drive pulses.
 9. The method ofclaim 7 wherein configuring the power supply controller to form theplurality of drive pulses within the at least one set includesconfiguring the power supply controller to form the plurality of drivepulses to generate a triangle shaped signal envelope.
 10. The method ofclaim 7 wherein configuring the power supply controller to form theplurality of drive pulses within the at least one set includesconfiguring the power supply controller to form each drive pulse of theplurality of drive pulses to have a width that is greater than anadjacent drive pulse.
 11. The method of claim 7 wherein configuring thepower supply controller to organize output drive pulses of the powersupply controller into the plurality of sets includes configuring thepower supply controller to space the plurality of sets apart in time bya time period of at least one drive pulse.
 12. The method of claim 7wherein configuring the power supply controller to organize output drivepulses of the power supply controller into the plurality of setsincludes configuring the power supply controller to organize the outputdrive pulses into the plurality of sets responsively to a control signalrepresentative of an output voltage increasing from a first value to asecond value.
 13. The method of claim 7 wherein configuring the powersupply controller to form the plurality of drive pulses within the atleast one set includes configuring the power supply controller to forman asymmetrical reference signal and to use the asymmetrical referencesignal to control the pulse widths.
 14. The method of claim 13 furtherincluding configuring the power supply controller to use an asymmetricalreference voltage.
 15. A power controller semiconductor devicecomprising: a control block coupled to generate an asymmetricalreference signal having a value that varies over a time interval whereinthe time interval is greater than a switching cycle of the powercontroller; and a PWM controller coupled to receive the asymmetricalreference signal and generate during the time interval a set of drivepulses that includes a plurality of drive pulses, the plurality drivepulses having widths that increase successively over the time intervalwherein the PWM controller is configured to use the plurality of drivepulses to control a power switch to generate a current having anasymmetrical signal envelope that increases in amplitude responsively toall of the plurality of drive pulses.
 16. The power controllersemiconductor device of claim 15 wherein the control block coupled togenerate the asymmetrical reference signal includes the control blockcoupled to generate the asymmetrical reference signal responsively to acontrol signal representative of an output voltage changing from a firstvalue to a second value.
 17. The power controller semiconductor deviceof claim 16 wherein the control block coupled to generate theasymmetrical reference signal includes the control block coupled togenerate an asymmetrical reference voltage.
 18. The method of claim 2further including configuring the power system controller to form thereference signal to be representative of the control signal and to usethe reference signal to control the power switch and regulate the outputvoltage to a desired value responsively to the control signal having avalue that is less than the second value; and configuring the controlblock to set the reference signal to a value at a beginning of a set ofdrive pulses that causes each drive pulse of the plurality of drivepulses that are formed during the set of drive pulses to have a widththat is greater than an immediately preceding drive pulse of theplurality of drive pulses.
 19. The method of claim 7 wherein configuringthe power supply controller to form the reference signal having thevalue that varies continuously over the time interval includesconfiguring the power supply controller to form the reference signal toincrease in value continuously over the time interval.
 20. The powercontroller semiconductor device of claim 15 wherein the control block isconfigured to form the reference signal to increase in valuecontinuously over the time interval.